The present invention relates to datapath processing—for example, to apparatus and methods for high-performance datapath processing. The present invention is particularly useful for programmable integrated circuit devices, such as programmable logic devices (PLDs).
Many modern processing applications (e.g., packet processing, digital signal processing, or digital image processing) require both high performance and high flexibility. Existing processing devices, however, typically provide inflexible pipeline architectures that have several shortcomings. For example, pipelined processing devices are limited in their speed. To guarantee that each stage executes properly, a pipelined device can only operate as fast as the slowest stage of the pipeline. Moreover, such pipelines typically operate in a sequential manner, whereby each unit of data must pass through each stage of the pipeline regardless of processing variables (e.g., the type of data or the mode of operation). This inflexibility can cause inefficiencies and delays. While some systems attempt to provide both the performance of hardware with dedicated hardware blocks, and the flexibility of software with a processor, these systems are often limited by the inflexible nature of the dedicated hardware blocks. Moreover, the inflexible nature of the hardware blocks typically requires extensive design efforts to develop each data processing sequence.